1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a source-drain impurity diffusion region by implanting As ions in a MOS memory cell having a LDD (Lightly Doped Drain) structure.
2. Description of the Prior Art
Conventionally, there has been proposed a method for manufacturing a MOS memory cell shown in FIG. 5 as one of methods for forming a gate construction having a LDD structure.
As shown in FIG. 5 (a), a gate electrode (53) is formed on a Si substrate (51) through a gate oxide film (52). A SiO.sub.2 film as a side wall material is deposited on the gate electrode (53). RIE is carried out to form a SiO.sub.2 side wall (54).
Then, As ions (55) are implanted as impurities on the whole surface. A NSG film (56) is deposited in order to prevent out diffusion. Thereafter, a heat treatment is carried out for 60 minutes at a middle temperature, for example, of about 800.degree. C. so as to diffuse the impurities. Consequently, an impurity diffusion layer (51a) is formed [see FIG. 5 (b)].
A BPSG film (58) is deposited on the whole surface in order to reduce a level difference between layers. The heat treatment is carried out for 30 minutes at a high temperature, for example, of about 950.degree. C. so as to adjust a shape. Thus, the surface is made flat [see FIG. 5 (c)].
Then, a contact hole is formed for metal wiring, so that an element is produced.
There has been proposed another method for forming an impurity diffusion layer (51a). More specifically, As ions (55) are implanted [see FIG. 6 (a)]. A middle temperature heat treatment is carried out for impurity diffusion. A NSG film (56) is deposited in order to prevent out diffusion. Then, a BPSG film (58) is deposited so as to reduce a level difference between layers. Thereafter, a high temperature heat treatment is carried out in order to adjust a shape [see FIG. 6 (b)].
Referring to a prior art shown in FIG. 6, especially, oxide in a SiO.sub.2 film (60) is implanted in the Si substrate (51) together with the As ions (55). Consequently, crystal defects occur on the Si substrate (51). Also in the case where the middle temperature heat treatment is carried out to form the impurity diffusion region (51a), the crystal defects are not eliminated.
Referring to a prior art shown in FIG. 5, when the middle temperature heat treatment is carried out to form the impurity diffusion region (51a), crystal defects (59) occur owing to the cluster of impurities introduced into the impurity diffusion region (51a). Thus, an electric leak is caused so that a yield may be reduced.